Field
The disclosed embodiments relate to power management in computer systems. More specifically, the disclosed embodiments relate to techniques for reducing power consumption by overriding latency tolerance reporting (LTR) values in components of computer systems.
Related Art
A modern computer system typically includes a motherboard containing a processor and memory, along with a set of peripheral components connected to the motherboard via a variety of interfaces. For example, a Serial Advanced Technology Attachment (SATA) interface may facilitate data transfer between a storage device (e.g., hard disk drive, optical drive, solid-state drive, hybrid hard drive, etc.) and the motherboard, while a Peripheral Component Interconnect Express (PCIe) bus may enable communication between the motherboard and a number of integrated and/or add-on peripheral components.
In addition, use of the interfaces by the peripheral components may affect the power consumption of the computer system. For example, a Central Processing Unit (CPU) of the computer system may not be able to enter a low-power state while the CPU is executing and/or a PCIe interface is used by a peripheral component in the computer system. The CPU may further be kept from entering and/or staying in the low-power state if the peripheral component does not have the capability to provide a Latency Tolerance Reporting (LTR) value to the CPU and/or root complex of the PCIe interface. As a result, the CPU may be required to stay in a higher-power state to satisfy a default and/or minimum latency tolerance for the peripheral component, even if the peripheral component can tolerate a higher latency from the CPU.
Consequently, power consumption in computer systems may be improved by assessing latency tolerances of peripheral components in the computer systems and operating processors in the computer systems based on the assessed latency tolerances.